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| Zero-Drift, Single-Supply, Rail-to-Rail Input/Output Operational Amplifiers AD8551/AD8552/AD8554 FEATURES Low offset voltage: 1 V Input offset drift: 0.005 V/C Rail-to-rail input and output swing 5 V/2.7 V single-supply operation High gain, CMRR, PSRR: 130 dB Ultralow input bias current: 20 pA Low supply current: 700 A/op amp Overload recovery time: 50 s No external capacitors required PIN CONFIGURATIONS NC -IN A +IN A V- 1 8 AD8551 4 5 NC = NO CONNECT Figure 1. 8-Lead MSOP (RM Suffix) NC 1 -IN A 2 +IN A 3 V- 4 8 NC AD8551 7 V+ 6 OUT A 01101-002 APPLICATIONS Temperature sensors Pressure sensors Precision current sensing Strain gage amplifiers Medical instrumentation Thermocouple amplifiers 5 NC NC = NO CONNECT Figure 2. 8-Lead SOIC (R Suffix) OUT A -IN A +IN A V- 1 8 V+ OUT B -IN B +IN B AD8552 4 5 Figure 3. 8-Lead TSSOP (RU Suffix) GENERAL DESCRIPTION This family of amplifiers has ultralow offset, drift, and bias current. The AD8551, AD8552, and AD8554 are single, dual, and quad amplifiers featuring rail-to-rail input and output swings. All are guaranteed to operate from 2.7 V to 5 V with a single supply. The AD855x family provides the benefits previously found only in expensive auto-zeroing or chopper-stabilized amplifiers. Using Analog Devices, Inc. topology, these new zero-drift amplifiers combine low cost with high accuracy. No external capacitors are required. With an offset voltage of only 1 V and drift of 0.005 V/C, the AD855x are perfectly suited for applications in which error sources cannot be tolerated. Temperature, position and pressure sensors, medical equipment, and strain gage amplifiers benefit greatly from nearly zero drift over their operating temperature range. The rail-to-rail input and output swings provided by the AD855x family make both high-side and low-side sensing easy. The AD855x family is specified for the extended industrial/auto motive temperature range (-40C to +125C). The AD8551 single amplifier is available in 8-lead MSOP and 8-lead narrow SOIC packages. The AD8552 dual amplifier is available in 8-lead narrow SOIC and 8-lead TSSOP surface-mount packages. The AD8554 quad is available in 14-lead narrow SOIC and 14-lead TSSOP packages. OUT A 1 -IN A 2 +IN A 3 V- 4 8 V+ AD8552 7 OUT B 01101-004 6 -IN B 5 +IN B Figure 4. 8-Lead SOIC (R Suffix) OUT A -IN A +IN A V+ +IN B -IN B OUT B 1 14 OUT D -IN D +IN D V- +IN C -IN C OUT C AD8554 7 8 Figure 5. 14-Lead TSSOP (RU Suffix) OUT A 1 -IN A 2 +IN A 3 V+ 4 +IN B 5 -IN B 6 OUT B 7 14 OUT D 13 -IN D 12 +IN D AD8554 11 V- 10 +IN C 01101-006 9 -IN C 8 OUT C Figure 6. 14-Lead SOIC (R Suffix) Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)1999-2007 Analog Devices, Inc. All rights reserved. 01101-005 01101-003 01101-001 NC V+ OUT A NC AD8551/AD8552/AD8554 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Pin Configurations ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics............................................................. 3 Absolute Maximum Ratings............................................................ 5 Thermal Characteristics .............................................................. 5 ESD Caution.................................................................................. 5 Typical Performance Characteristics ............................................. 6 Functional Description .................................................................. 14 Amplifier Architecture .............................................................. 14 Basic Auto-Zero Amplifier Theory.......................................... 14 High Gain, CMRR, PSRR.......................................................... 16 Maximizing Performance Through Proper Layout ............... 16 1/f Noise Characteristics ........................................................... 16 Intermodulation Distortion ...................................................... 17 Broadband and External Resistor Noise Considerations...... 18 Output Overdrive Recovery...................................................... 18 Input Overvoltage Protection ................................................... 18 Output Phase Reversal............................................................... 19 Capacitive Load Drive ............................................................... 19 Power-Up Behavior .................................................................... 19 Applications..................................................................................... 20 5 V Precision Strain Gage Circuit ............................................ 20 3 V Instrumentation Amplifier ................................................ 20 High Accuracy Thermocouple Amplifier............................... 21 Precision Current Meter............................................................ 21 Precision Voltage Comparator.................................................. 21 Outline Dimensions ....................................................................... 22 Ordering Guide .......................................................................... 23 REVISION HISTORY 3/07--Rev. B to Rev. C Changes to Specifications Section.................................................. 3 2/07--Rev. A to Rev. B Updated Format..................................................................Universal Changes to Figure 54...................................................................... 16 Deleted Spice Model Section......................................................... 19 Deleted Figure 63, Renumbered Sequentially ............................ 19 Changes to Ordering Guide .......................................................... 24 11/02--Rev. 0 to Rev. A Edits to Figure 60............................................................................ 16 Updated Outline Dimensions ....................................................... 20 Rev. C | Page 2 of 24 AD8551/AD8552/AD8554 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VS = 5 V, VCM = 2.5 V, VO = 2.5 V, TA = 25C, unless otherwise noted. Table 1. Parameter INPUT CHARACTERISTICS Offset Voltage Input Bias Current AD8551/AD8554 AD8552 AD8552 Input Offset Current AD8551/AD8554 AD8552 AD8552 Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain1 Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage High Symbol VOS -40C TA +125C IB -40C TA +125C -40C TA +85C -40C TA +125C IOS -40C TA +125C -40C TA +85C -40C TA +125C CMRR AVO VOS/T VOH VCM = 0 V to +5 V -40C TA +125C RL = 10 k, VO = 0.3 V to 4.7 V -40C TA +125C -40C TA +125C RL = 100 k to GND RL = 100 k to GND @ -40C to +125C RL = 10 k to GND RL = 10 k to GND @ -40C to +125C RL = 100 k to V+ RL = 100 k to V+ @ -40C to +125C RL = 10 k to V+ RL = 10 k to V+ @ -40C to +125C -40C to +125C Output Current POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Overload Recovery Time Gain Bandwidth Product NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density 1 Conditions Min Typ 1 10 1.0 160 2.5 20 150 30 150 Max 5 10 50 1.5 300 4 70 200 150 400 5 Unit V V pA nA pA nA pA pA pA pA V dB dB dB dB V/C V V V V mV mV mV mV mA mA mA mA dB dB A A V/s ms MHz V p-p V p-p nV/Hz fA/Hz 0 120 115 125 120 140 130 145 135 0.005 4.998 4.997 4.98 4.975 1 2 10 15 50 40 30 15 130 130 850 1000 0.4 0.05 1.5 1.0 0.32 42 2 0.04 4.99 4.99 4.95 4.95 Output Voltage Low VOL 10 10 30 30 Output Short-Circuit Limit Current ISC IO -40C to +125C PSRR ISY VS = 2.7 V to 5.5 V -40C TA +125C VO = 0 V -40C TA +125C RL = 10 k 25 120 115 975 1075 SR GBP en p-p en p-p en in 0.3 0 Hz to 10 Hz 0 Hz to 1 Hz f = 1 kHz f = 10 Hz Gain testing is dependent upon test bandwidth. Rev. C | Page 3 of 24 AD8551/AD8552/AD8554 VS = 2.7 V, VCM = 1.35 V, VO = 1.35 V, TA = 25C, unless otherwise noted. Table 2. Parameter INPUT CHARACTERISTICS Offset Voltage Input Bias Current AD8551/AD8554 AD8552 AD8552 Input Offset Current AD8551/AD8554 AD8552 AD8552 Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain 1 Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage High Symbol VOS -40C TA +125C IB -40C TA +125C -40C TA +85C -40C TA +125C IOS -40C TA +125C -40C TA +85C -40C TA +125C CMRR AVO VOS/T VOH VCM = 0 V to 2.7 V -40C TA +125C RL = 10 k, VO = 0.3 V to 2.4 V -40C TA +125C -40C TA +125C RL = 100 k to GND RL = 100 k to GND @ -40C to +125C RL = 10 k to GND RL = 10 k to GND @ -40C to +125C RL = 100 k to V+ RL = 100 k to V+ @ -40C to +125C RL = 10 k to V+ RL = 10 k to V+ @ -40C to +125C -40C to +125C Output Current POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Overload Recovery Time Gain Bandwidth Product NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density 1 Conditions Min Typ 1 10 1.0 160 2.5 10 150 30 150 Max 5 10 50 1.5 300 4 50 200 150 400 2.7 Unit V V pA nA pA nA pA pA pA pA V dB dB dB dB V/C V V V V mV mV mV mV mA mA mA mA dB dB A A V/s ms MHz V p-p nV/Hz fA/Hz 0 115 110 110 105 130 130 140 130 0.005 2.697 2.696 2.68 2.675 1 2 10 15 15 10 10 5 130 130 750 950 0.5 0.05 1 1.6 75 2 0.04 2.685 2.685 2.67 2.67 Output Voltage Low VOL 10 10 20 20 Short-Circuit Limit ISC IO -40C to +125C PSRR ISY VS = 2.7 V to 5.5 V -40C TA +125C VO = 0 V -40C TA +125C RL = 10 k 10 120 115 900 1000 SR GBP en p-p en in 0 Hz to 10 Hz f = 1 kHz f = 10 Hz Gain testing is dependent upon test bandwidth. Rev. C | Page 4 of 24 AD8551/AD8552/AD8554 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Voltage Input Voltage Differential Input Voltage1 ESD (Human Body Model) Output Short-Circuit Duration to GND Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature Range (Soldering, 60 sec) 1 THERMAL CHARACTERISTICS Rating 6V GND to VS + 0.3 V 5.0 V 2000 V Indefinite -65C to +150C -40C to +125C -65C to +150C 300C Table 4. Package Type 8-Lead MSOP (RM) 8-Lead TSSOP (RU) 8-Lead SOIC (R) 14-Lead TSSOP (RU) 14-Lead SOIC (R) JA 190 240 158 180 120 JC 44 43 43 36 36 Unit C/W C/W C/W C/W C/W ESD CAUTION Differential input voltage is limited to 5.0 V or the supply voltage, whichever is less. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. C | Page 5 of 24 AD8551/AD8552/AD8554 TYPICAL PERFORMANCE CHARACTERISTICS 180 160 NUMBER OF AMPLIFIERS 180 VSY = 2.7V VCM = 1.35V TA = 25C NUMBER OF AMPLIFIERS 160 140 120 100 80 60 40 20 01101-007 VSY = 5V VCM = 2.5V TA = 25C 140 120 100 80 60 40 20 0 -2.5 -1.5 -0.5 0.5 1.5 OFFSET VOLTAGE (V) 2.5 -1.5 0.5 -0.5 1.5 OFFSET VOLTAGE (V) 2.5 Figure 7. Input Offset Voltage Distribution at 2.7 V 50 40 Figure 10. Input Offset Voltage Distribution at 5 V 12 VSY = 5V TA = -40C, +25C, +85C +85C 10 VSY = 5V VCM = 2.5V TA = -40C TO +125C INPUT BIAS CURRENT (pA) NUMBER OF AMPLIFIERS 30 20 10 +25C 0 -10 -20 01101-008 8 6 -40C 4 2 0 1 2 3 4 INPUT COMMON-MODE VOLTAGE (V) 5 0 1 2 3 4 INPUT OFFSET DRIFT (nV/C) 5 6 Figure 8. Input Bias Current vs. Common-Mode Voltage 1500 1000 10k Figure 11. Input Offset Voltage Drift Distribution at 5 V VSY = 5V TA = 125C VSY = 5V TA = 25C 1k INPUT BIAS CURRENT (pA) OUTPUT VOLTAGE (mV) 500 0 -500 -1000 -1500 -2000 100 10 SOURCE SINK 1 01101-009 0 1 2 3 4 INPUT COMMON-MODE VOLTAGE (V) 5 0.001 0.01 0.1 1 LOAD CURRENT (mA) 10 100 Figure 9. Input Bias Current vs. Common-Mode Voltage Figure 12. Output Voltage to Supply Rail vs. Load Current at 5 V Rev. C | Page 6 of 24 01101-012 0.1 0.0001 01101-011 -30 0 01101-010 0 -2.5 AD8551/AD8552/AD8554 10k 800 SUPPLY CURRENT PER AMPLIFIER (A) VSY = 2.7V TA = 25C 1k OUTPUT VOLTAGE (mV) TA = +25C 700 600 500 400 300 200 100 01101-016 100 10 SOURCE SINK 1 01101-013 0.1 0.0001 0.001 0.01 0.1 1 LOAD CURRENT (mA) 10 100 0 0 1 2 3 4 SUPPLY VOLTAGE (V) 5 6 Figure 13. Output Voltage to Supply Rail vs. Load Current at 2.7 V 0 VCM = 2.5V VSY = 5V Figure 16. Supply Current per Amplifier vs. Supply Voltage 60 50 40 VSY = 2.7V CL = 0pF RL = 0 45 90 135 180 225 270 PHASE SHIFT (Degrees) PHASE SHIFT (Degrees) 01101-018 01101-017 INPUT BIAS CURRENT (pA) OPEN-LOOP GAIN (dB) 01101-014 -250 30 20 10 0 -10 -20 -30 -500 -750 -1000 -75 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 150 -40 10k 100k 1M FREQUENCY (Hz) 10M 100M Figure 14. Input Bias Current vs. Temperature 1.0 Figure 17. Open-Loop Gain and Phase Shift vs. Frequency at 2.7 V 60 VCM = 2.5V VSY = 5V 0.8 SUPPLY CURRENT (mA) 50 5V 2.7V OPEN-LOOP GAIN (dB) 40 30 20 10 0 -10 -20 -30 01101-015 VSY = 5V CL = 0pF RL = 0 45 90 135 180 225 270 0.6 0.4 0.2 0 -75 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 150 -40 10k 100k 1M FREQUENCY (Hz) 10M 100M Figure 15. Supply Current vs. Temperature Figure 18. Open-Loop Gain and Phase Shift vs. Frequency at 5 V Rev. C | Page 7 of 24 AD8551/AD8552/AD8554 60 50 AV = -100 300 40 VSY = 2.7V CL = 0pF RL = 2k OUTPUT IMPEDANCE () VSY = 5V 270 240 210 180 150 120 90 60 30 01101-019 CLOSED-LOOP GAIN (dB) 30 20 10 0 -10 -20 -30 -40 100 AV = -10 AV = +1 AV = 100 AV = 10 AV = 1 1k 10k 100k FREQUENCY (Hz) 1M 10M 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 19. Closed-Loop Gain vs. Frequency at 2.7 V 60 50 AV = -100 Figure 22. Output Impedance vs. Frequency at 5 V VSY = 2.7V CL = 300pF RL = 2k AV = 1 40 CLOSED-LOOP GAIN (dB) VSY = 5V CL = 0pF RL = 2k 30 20 10 0 -10 -20 -30 AV = -10 AV = +1 2s 1k 500mV 10k 100k FREQUENCY (Hz) 1M 10M Figure 20. Closed-Loop Gain vs. Frequency at 5 V 300 270 240 VSY = 2.7V 01101-020 -40 100 Figure 23. Large Signal Transient Response at 2.7 V VSY = 5V CL = 300pF RL = 2k AV = 1 OUTPUT IMPEDANCE () 210 180 150 120 90 60 30 0 100 AV = 100 AV = 10 AV = 1 01101-024 5s 1V 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 21. Output Impedance vs. Frequency at 2.7 V 01101-021 Figure 24. Large Signal Transient Response at 5 V Rev. C | Page 8 of 24 01101-023 01101-022 0 100 AD8551/AD8552/AD8554 RL = AV = 1 VSY = 1.35V CL = 50pF 45 40 SMALL SIGNAL OVERSHOOT (%) VSY = 2.5V RL = 2k TA = 25C 35 30 25 20 15 10 5 100 1k CAPACITANCE (pF) 10k 01101-028 01101-030 01101-029 +OS -OS 5s 50mV 01101-025 0 10 Figure 25. Small Signal Transient Response at 2.7 V VSY = 2.5V CL = 50pF Figure 28. Small Signal Overshoot vs. Load Capacitance at 5 V RL = AV = 1 0V VIN VSY = 2.5V VIN = -200mV p-p (RET TO GND) CL = 0pF RL = 10k AV = -100 VOUT 01101-026 0V 5s 50mV 20s 1V BOTTOM SCALE: 1V/DIV TOP SCALE: 200mV/DIV Figure 26. Small Signal Transient Response at 5 V 50 45 SMALL SIGNAL OVERSHOOT (%) Figure 29. Positive Overvoltage Recovery 40 35 30 25 20 15 10 5 VSY = 1.35V RL = 2k TA = 25C VIN 0V VSY = 2.5V VIN = 200mV p-p (RET TO GND) CL = 0pF RL = 10k AV = -100 +OS 0V -OS VOUT 20s 01101-027 1V 0 10 100 1k CAPACITANCE (pF) 10k BOTTOM SCALE: 1V/DIV TOP SCALE: 200mV/DIV Figure 27. Small Signal Overshoot vs. Load Capacitance at 2.7 V Figure 30. Negative Overvoltage Recovery Rev. C | Page 9 of 24 AD8551/AD8552/AD8554 VS = 2.5V RL = 2k AV = -100 VIN = 60mV p-p 140 VSY = 1.35V 120 100 PSRR (dB) 80 60 +PSRR 40 20 0 100 -PSRR 200s 1V 01101-031 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 31. No Phase Reversal 140 120 100 140 120 100 Figure 34. PSRR vs. Frequency at 1.35 V VSY = 2.7V VSY = 2.5V CMRR (dB) PSRR (dB) 80 60 40 20 0 100 80 +PSRR 60 40 -PSRR 20 0 100 01101-032 1k 10k 100k FREQUENCY (Hz) 1M 10M 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 32. CMRR vs. Frequency at 2.7 V 140 120 Figure 35. PSRR vs. Frequency at 2.5 V 3.0 VSY = 5V 2.5 OUTPUT SWING (V p-p) 100 VSY = 1.35V RL = 2k AV = 1 THD+N < 1% TA = 25C 2.0 CMRR (dB) 80 60 40 20 0 100 1.5 1.0 0.5 01101-033 1k 10k 100k FREQUENCY (Hz) 1M 10M 1k 10k FREQUENCY (Hz) 100k 1M Figure 33. CMRR vs. Frequency at 5 V Figure 36. Maximum Output Swing vs. Frequency at 2.7 V Rev. C | Page 10 of 24 01101-036 0 100 01101-035 01101-034 AD8551/AD8552/AD8554 5.5 5.0 4.5 OUTPUT SWING (V p-p) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 1k 10k FREQUENCY (Hz) 100k VSY = 2.5V RL = 2k AV = 1 THD+N < 1% TA = 25C en (nV/Hz) 182 156 130 104 78 52 26 VSY = 2.7V RS = 0 1M Figure 37. Maximum Output Swing vs. Frequency at 5 V VSY = 1.35V AV = 10000 01101-037 0 100 0 0.5 1.0 1.5 FREQUENCY (kHz) 2.0 2.5 Figure 40. Voltage Noise Density at 2.7 V from 0 Hz to 2.5 kHz 112 96 80 64 48 32 01101-038 VSY = 2.7V RS = 0 0V en (nV/Hz) 16 01101-041 01101-042 1s 2mV 0 5 10 15 FREQUENCY (kHz) 20 25 Figure 38. 0.1 Hz to 10 Hz Noise at 2.7 V VSY = 2.5V AV = 10000 Figure 41. Voltage Noise Density at 2.7 V from 0 Hz to 25 kHz VSY = 5V RS = 0 91 78 65 52 39 26 01101-039 en (nV/Hz) 13 1s 2mV 0 0.5 1.0 1.5 FREQUENCY (kHz) 2.0 2.5 Figure 39. 0.1 Hz to 10 Hz Noise at 5 V Figure 42. Voltage Noise Density at 5 V from 0 Hz to 2.5 kHz Rev. C | Page 11 of 24 01101-040 AD8551/AD8552/AD8554 112 96 80 64 48 32 16 01101-043 VSY = 5V RS = 0 150 VSY = 2.7V TO 5.5V POWER SUPPLY REJECTION (dB) 145 en (nV/Hz) 140 135 130 0 5 10 15 FREQUENCY (kHz) 20 25 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 150 Figure 43. Voltage Noise Density at 5 V from 0 Hz to 25 kHz 50 40 SHORT-CIRCUIT CURRENT (mA) Figure 45. Power Supply Rejection vs. Temperature 168 144 120 96 72 48 24 VSY = 5V RS = 0 VSY = 2.7V 30 20 10 0 -10 -20 -30 -40 ISC- en (nV/Hz) ISC+ 01101-044 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 150 Figure 44. Voltage Noise Density at 5 V from 0 Hz to 10 Hz Figure 46. Output Short-Circuit Current vs. Temperature Rev. C | Page 12 of 24 01101-046 0 5 FREQUENCY (Hz) 10 -50 -75 01101-045 125 -75 AD8551/AD8552/AD8554 100 80 SHORT-CIRCUIT CURRENT (mA) OUTPUT VOLTAGE TO SUPPLY RAIL (mV) VSY = 5.0V ISC- 250 225 200 175 150 125 100 75 50 25 0 -75 VSY = 5.0V 60 40 20 0 -20 -40 -60 -80 RL = 1k ISC+ RL = 100k RL = 10k -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 150 01101-049 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 150 01101-047 -100 -75 Figure 47. Output Short-Circuit Current vs. Temperature 250 OUTPUT VOLTAGE TO SUPPLY RAIL (mV) Figure 49. Output Voltage to Supply Rail vs. Temperature 225 200 175 150 125 100 75 50 25 VSY = 2.7V RL = 1k RL = 100k RL = 10k -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 150 01101-048 0 -75 Figure 48. Output Voltage to Supply Rail vs. Temperature Rev. C | Page 13 of 24 AD8551/AD8552/AD8554 FUNCTIONAL DESCRIPTION The AD855x family of amplifiers are high precision, rail-to-rail operational amplifiers that can be run from a single-supply voltage. Their typical offset voltage of less than 1 V allows these amplifiers to be easily configured for high gains without risk of excessive output voltage errors. The extremely small temperature drift of 5 nV/C ensures a minimum of offset voltage error over its entire temperature range of -40C to +125C, making the AD855x amplifiers ideal for a variety of sensitive measurement applications in harsh operating environments, such as underhood and braking/suspension systems in automobiles. The AD855x family are CMOS amplifiers and achieve their high degree of precision through auto-zero stabilization. This autocorrection topology allows the AD855x to maintain its low offset voltage over a wide temperature range and over its operating lifetime. BASIC AUTO-ZERO AMPLIFIER THEORY Autocorrection amplifiers are not a new technology. Various IC implementations have been available for more than 15 years with some improvements made over time. The AD855x design offers a number of significant performance improvements over previous versions while attaining a very substantial reduction in device cost. This section offers a simplified explanation of how the AD855x is able to offer extremely low offset voltages and high open-loop gains. As noted in the Amplifier Architecture section, each AD855x op amp contains two internal amplifiers. One is used as the primary amplifier, the other as an autocorrection, or nulling, amplifier. Each amplifier has an associated input offset voltage that can be modeled as a dc voltage source in series with the noninverting input. In Figure 50 and Figure 51 these are labeled as VOSX, where x denotes the amplifier associated with the offset: A for the nulling amplifier and B for the primary amplifier. The open-loop gain for the +IN and -IN inputs of each amplifier is given as AX. Both amplifiers also have a third voltage input with an associated open-loop gain of BX. There are two modes of operation determined by the action of two sets of switches in the amplifier: an auto-zero phase and an amplification phase. AMPLIFIER ARCHITECTURE Each AD855x op amp consists of two amplifiers, a main amplifier and a secondary amplifier, used to correct the offset voltage of the main amplifier. Both consist of a rail-to-rail input stage, allowing the input common-mode voltage range to reach both supply rails. The input stage consists of an NMOS differential pair operating concurrently with a parallel PMOS differential pair. The outputs from the differential input stages are combined in another gain stage whose output is used to drive a rail-to-rail output stage. The wide voltage swing of the amplifier is achieved by using two output transistors in a common-source configuration. The output voltage range is limited by the drain-to-source resistance of these transistors. As the amplifier is required to source or sink more output current, the rDS of these transistors increases, raising the voltage drop across these transistors. Simply put, the output voltage does not swing as close to the rail under heavy output current conditions as it does with light output current. This is a characteristic of all rail-to-rail output amplifiers. Figure 12 and Figure 13 show how close the output voltage can get to the rails with a given output current. The output of the AD855x is short-circuit protected to approximately 50 mA of current. The AD855x amplifiers have exceptional gain, yielding greater than 120 dB of open-loop gain with a load of 2 k. Because the output transistors are configured in a common-source configuration, the gain of the output stage, and thus the openloop gain of the amplifier, is dependent on the load resistance. Open-loop gain decreases with smaller load resistances. This is another characteristic of rail-to-rail output amplifiers. Auto-Zero Phase In this phase, all A switches are closed and all B switches are opened. Here, the nulling amplifier is taken out of the gain loop by shorting its two inputs together. Of course, there is a degree of offset voltage, shown as VOSA, inherent in the nulling amplifier which maintains a potential difference between the +IN and -IN inputs. The nulling amplifier feedback loop is closed through B2 and VOSA appears at the output of the nulling amp and on CM1, an internal capacitor in the AD855x. Mathematically, this is expressed in the time domain as VOA[t] = AAVOSA[t] - BBAVOA[t] which can be expressed as (1) VOA [t ] = AAVOSA [t ] 1 + BA (2) This demonstrates that the offset voltage of the nulling amplifier times a gain factor appears at the output of the nulling amplifier and, thus, on the CM1 capacitor. Rev. C | Page 14 of 24 AD8551/AD8552/AD8554 VIN+ VIN- B A VOSA + AA -BA A VOA AB BB B CM2 VOUT VOA [t ] = AAVIN [t ] + or AA (1 + BA )VOSA - AA BAVOSA 1 + BA (6) VNB CM1 01101-050 V VOA [t ] = AA VIN [t ] + OSA 1 + BA (7) VNA Figure 50. Auto-Zero Phase of the AD855x Amplification Phase When the B switches close and the A switches open for the amplification phase, this offset voltage remains on CM1 and, essentially, corrects any error from the nulling amplifier. The voltage across CM1 is designated as VNA. Furthermore, VIN is designated as the potential difference between the two inputs to the primary amplifier, or VIN = (VIN+ - VIN-). Thus, the nulling amplifier can be expressed as VOA [t ] = A A (V IN [t ] - VOSA [t ]) - B AVNA [t ] VIN+ VIN- B VOSA + A AA -BA A VOA AB BB B CM2 VOUT From these equations, the auto-zeroing action becomes evident. Note the VOS term is reduced by a 1 + BA factor. This shows how the nulling amplifier has greatly reduced its own offset voltage error even before correcting the primary amplifier. This results in the primary amplifier output voltage becoming the voltage at the output of the AD855x amplifier. It is equal to VOUT [t ] = AB (VIN [t ] + VOSB ) + BBVNB (8) In the amplification phase, VOA = VNB, so this can be rewritten as V VOUT [t ] = A B VIN [t ] + A B VOSB + B B A A VIN [t ] + OSB 1 + BA Combining terms, VOUT [t ] = VIN [t ](AB + AB BB ) + AA BAVOSA + ABVOSA 1 + BA (10) (9) (3) The AD855x architecture is optimized in such a way that VNB CM1 01101-051 AA = AB and BA = B and BA >> 1 B B BB B VNA Also, the gain product of AABBB is much greater than ABB. These allow Equation 10 to be simplified to VOUT [t ] VIN [t ]AA BA + AA (VOSA + VOSB ) Figure 51. Output Phase of the Amplifier (11) Because A is now open and there is no place for CM1 to discharge, the voltage (VNA), at the present time (t), is equal to the voltage at the output of the nulling amp (VOA) at the time when A was closed. If the period of the autocorrection switching frequency is labeled tS, then the amplifier switches between phases every 0.5 x tS. Therefore, in the amplification phase 1 VNA [t ] = VNA t - t S 2 (4) Most obvious is the gain product of both the primary and nulling amplifiers. This AABBA term is what gives the AD855x its extremely high open-loop gain. To understand how VOSA and VOSBB relate to the overall effective input offset voltage of the complete amplifier, establish the generic amplifier equation of VOUT = k x (VIN + VOS , EFF ) (12) where k is the open-loop gain of an amplifier and VOS, EFF is its effective offset voltage. Putting Equation 12 into the form of Equation 11 gives VOUT [t ] VIN [t ]AA BA + VOS , EFF AA BA (13) Substituting Equation 4 and Equation 2 into Equation 3 yields 1 AA B AVOSA t - t S 2 VOA [t ] = AAVIN [t ] + AAVOSA [t ] - 1 + BA (5) Thus, it is evident that VOS , EFF VOSA + VOSB BA (14) For the sake of simplification, assume that the autocorrection frequency is much faster than any potential change in VOSA or VOSB. This is a valid assumption because changes in offset voltage are a function of temperature variation or long-term wear time, both of which are much slower than the auto-zero clock frequency of the AD855x. This effectively renders VOS time invariant; therefore, Equation 5 can be rearranged and rewritten as B The offset voltages of both the primary and nulling amplifiers are reduced by the Gain Factor BA. This takes a typical input offset voltage from several millivolts down to an effective input offset voltage of submicrovolts. This autocorrection scheme is the outstanding feature of the AD855x series that continues to Rev. C | Page 15 of 24 AD8551/AD8552/AD8554 earn the reputation of being among the most precise amplifiers available on the market. Other potential sources of offset error are thermoelectric voltages on the circuit board. This voltage, also called Seebeck voltage, occurs at the junction of two dissimilar metals and is proportional to the temperature of the junction. The most common metallic junctions on a circuit board are solder-toboard trace and solder-to-component lead. Figure 54 shows a cross-section of the thermal voltage error sources. If the temperature of the PC board at one end of the component (TA1) is different from the temperature at the other end (TA2), the resulting Seebeck voltages are not equal, resulting in a thermal voltage error. This thermocouple error can be reduced by using dummy components to match the thermoelectric error source. Placing the dummy component as close as possible to its partner ensures both Seebeck voltages are equal, thus canceling the thermocouple error. Maintaining a constant ambient temperature on the circuit board further reduces this error. The use of a ground plane helps distribute heat throughout the board and reduces EMI noise pickup. COMPONENT LEAD VSC1 + VTS1 + SURFACE-MOUNT COMPONENT + HIGH GAIN, CMRR, PSRR Common-mode and power supply rejection are indications of the amount of offset voltage an amplifier has as a result of a change in its input common-mode or power supply voltages. As shown in the previous section, the autocorrection architecture of the AD855x allows it to quite effectively minimize offset voltages. The technique also corrects for offset errors caused by common-mode voltage swings and power supply variations. This results in superb CMRR and PSRR figures in excess of 130 dB. Because the autocorrection occurs continuously, these figures can be maintained across the entire temperature range of the device, from -40C to +125C. MAXIMIZING PERFORMANCE THROUGH PROPER LAYOUT To achieve the maximum performance of the extremely high input impedance and low offset voltage of the AD855x, care is needed in laying out the circuit board. The PC board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board reduces surface moisture and provides a humidity barrier, reducing parasitic resistance on the board. The use of guard rings around the amplifier inputs further reduces leakage currents. Figure 52 shows proper guard ring configuration, and Figure 53 shows the top view of a surface-mount layout. The guard ring does not need to be a specific width, but it should form a continuous loop around both inputs. By setting the guard ring voltage equal to the voltage at the noninverting input, parasitic capacitance is minimized as well. For further reduction of leakage currents, components can be mounted to the PC board using Teflon standoff insulators. VSC2 SOLDER + VTS2 PC BOARD TA1 COPPER TRACE TA2 IF TA1 TA2, THEN VTS1 + VSC1 VTS2 + VSC2 01101-054 Figure 54. Mismatch in Seebeck Voltages Causes Thermoelectric Voltage Error RF R1 VIN RS = R1 VOUT AD8551/ AD8552/ AD8554 AV = 1 + (RF/R1) 01101-055 VIN VOUT AD8552 VIN VOUT AD8552 NOTES 1. RS SHOULD BE PLACED IN CLOSE PROXIMITY AND ALIGNMENT TO R1 TO BALANCE SEEBECK VOLTAGES. VIN Figure 55. Using Dummy Components to Cancel Thermoelectric Voltage Errors VOUT 01101-052 AD8552 1/f NOISE CHARACTERISTICS Another advantage of auto-zero amplifiers is their ability to cancel flicker noise. Flicker noise, also known as 1/f noise, is noise inherent in the physics of semiconductor devices, and it increases 3 dB for every octave decrease in frequency. The 1/f corner frequency of an amplifier is the frequency at which the flicker noise is equal to the broadband noise of the amplifier. At lower frequencies, flicker noise dominates, causing higher degrees of error for sub-Hertz frequencies or dc precision applications. Figure 52. Guard Ring Layout and Connections to Reduce PC Board Leakage Currents R1 VIN1 R2 V+ AD8552 R2 R1 VIN2 GUARD RING VREF VREF V- Figure 53. Top View of AD8552 SOIC Layout with Guard Rings Rev. C | Page 16 of 24 01101-053 GUARD RING AD8551/AD8552/AD8554 Because the AD855x amplifiers are self-correcting op amps, they do not have increasing flicker noise at lower frequencies. In essence, low frequency noise is treated as a slowly varying offset error and is greatly reduced as a result of autocorrection. The correction becomes more effective as the noise frequency approaches dc, offsetting the tendency of the noise to increase exponentially as frequency decreases. This allows the AD855x to have lower noise near dc than standard low noise amplifiers that are susceptible to 1/f noise. 0 -20 -40 -60 -80 -100 -120 -140 VSY = 5V AV = 60dB INTERMODULATION DISTORTION The AD855x can be used as a conventional op amp for gain/ bandwidth combinations up to 1.5 MHz. The auto-zero correction frequency of the device is fixed at 4 kHz. Although a trace amount of this frequency feeds through to the output, the amplifier can be used at much higher frequencies. Figure 56 shows the spectral output of the AD8552 with the amplifier configured for unity gain and the input grounded. The 4 kHz auto-zero clock frequency appears at the output with less than 2 V of amplitude. Harmonics are also present, but at reduced levels from the fundamental auto-zero clock frequency. The amplitude of the clock frequency feedthrough is proportional to the closed-loop gain of the amplifier. Like other autocorrection amplifiers, at higher gains there is more clock frequency feedthrough. Figure 57 shows the spectral output with the amplifier configured for a gain of 60 dB. 0 -20 -40 -60 -80 -100 -120 -140 VSY = 5V AV = 0dB OUTPUT SIGNAL (dB) 0 1 2 3 4 5 6 FREQUENCY (kHz) 7 8 9 10 Figure 57. Spectral Analysis of AD855x Output with +60 dB Gain When an input signal is applied, the output contains some degree of intermodulation distortion (IMD). This is another characteristic feature of all autocorrection amplifiers. IMD appears as sum and difference frequencies between the input signal and the 4 kHz clock frequency (and its harmonics) and is at a level similar to, or less than, the clock feedthrough at the output. The IMD is also proportional to the closed-loop gain of the amplifier. Figure 58 shows the spectral output of an AD8552 configured as a high gain stage (+60 dB) with a 1 mV input signal applied. The relative levels of all IMD products and harmonic distortion add up to produce an output error of -60 dB relative to the input signal. At unity gain, these add up to only -120 dB relative to the input signal. 0 OUTPUT SIGNAL 1V rms @ 200Hz -20 VSY = 5V AV = 60dB OUTPUT SIGNAL (dB) OUTPUT SIGNAL (dB) -40 -60 -80 IMD < 100V rms 0 1 2 3 4 5 6 FREQUENCY (kHz) 7 8 9 10 01101-056 -100 Figure 56. Spectral Analysis of AD8552 Output in Unity Gain Configuration 0 1 2 3 4 5 6 FREQUENCY (kHz) 7 8 9 10 Figure 58. Spectral Analysis of AD8552 in High Gain with a 1 mV Input Signal For most low frequency applications, the small amount of autozero clock frequency feedthrough does not affect the precision of the measurement system. If it is desired, the clock frequency feedthrough can be reduced through the use of a feedback capacitor around the amplifier. However, this reduces the bandwidth of the amplifier. Figure 59 and Figure 60 show a configuration for reducing the clock feedthrough and the corresponding spectral analysis at the output. The -3 dB bandwidth of this configuration is 480 Hz. Rev. C | Page 17 of 24 01101-058 -120 01101-057 AD8551/AD8552/AD8554 3.3nF 100k 100 VIN = 1mV rms @ 200Hz Because the input current noise of the AD855x is very small, it does not become a dominant term unless RS is greater than 4 G, which is an impractical value of source resistance. The total noise (en, TOTAL) is expressed in volts per square root Hertz, and the equivalent rms noise over a certain bandwidth can be found as en = en,TOTAL x BW Figure 59. Reducing Autocorrection Clock Noise Using a Feedback Capacitor 0 VSY = 5V AV = 60dB -20 01101-059 (16) where BW is the bandwidth of interest in Hertz. OUTPUT OVERDRIVE RECOVERY The AD855x amplifiers have an excellent overdrive recovery of only 200 s from either supply rail. This characteristic is particularly difficult for autocorrection amplifiers because the nulling amplifier requires a nontrivial amount of time to error correct the main amplifier back to a valid output. Figure 29 and Figure 30 show the positive and negative overdrive recovery times for the AD855x. 0 1 2 3 4 5 6 FREQUENCY (kHz) 7 8 9 10 OUTPUT SIGNAL -40 -60 -80 -100 Figure 60. Spectral Analysis Using a Feedback Capacitor BROADBAND AND EXTERNAL RESISTOR NOISE CONSIDERATIONS The total broadband noise output from any amplifier is primarily a function of three types of noise: input voltage noise from the amplifier, input current noise from the amplifier, and Johnson noise from the external resistors used around the amplifier. Input voltage noise, or en, is strictly a function of the amplifier used. The Johnson noise from a resistor is a function of the resistance and the temperature. Input current noise, or in, creates an equivalent voltage noise proportional to the resistors used around the amplifier. These noise sources are not correlated with each other and their combined noise sums in a rootsquared-sum fashion. The full equation is given as 01101-060 -120 The output overdrive recovery for an autocorrection amplifier is defined as the time it takes for the output to correct to its final voltage from an overload state. It is measured by placing the amplifier in a high gain configuration with an input signal that forces the output voltage to the supply rail. The input voltage is then stepped down to the linear region of the amplifier, usually to halfway between the supplies. The time from the input signal stepdown to the output settling to within 100 V of its final value is the overdrive recovery time. INPUT OVERVOLTAGE PROTECTION Although the AD855x is a rail-to-rail input amplifier, exercise care to ensure that the potential difference between the inputs does not exceed 5 V. Under normal operating conditions, the amplifier corrects its output to ensure the two inputs are at the same voltage. However, if the device is configured as a comparator, or is under some unusual operating condition, the input voltages may be forced to different potentials. This can cause excessive current to flow through internal diodes in the AD855x used to protect the input stage against overvoltage. If either input exceeds either supply rail by more than 0.3 V, large amounts of current begin to flow through the ESD protection diodes in the amplifier. These diodes connect between the inputs and each supply rail to protect the input transistors against an electrostatic discharge event and are normally reverse-biased. However, if the input voltage exceeds the supply voltage, these ESD diodes become forward-biased. Without current limiting, excessive amounts of current can flow through these diodes, causing permanent damage to the device. If inputs are subjected to overvoltage, appropriate series resistors should be inserted to limit the diode current to less than 2 mA maximum. en _ TOTAL = en2 + 4kTrS + (in RS )2 [ ] 1 2 (15) Where: en = the input voltage noise density of the amplifier. in = the input current noise of the amplifier. RS = source resistance connected to the noninverting terminal. k = Boltzmann's constant (1.38 x 10-23 J/K). T = ambient temperature in Kelvin (K = 273.15 + C). The input voltage noise density (en) of the AD855x is 42 nV/Hz, and the input noise, in, is 2 fA/Hz. The en, TOTAL is dominated by the input voltage noise, provided the source resistance is less than 106 k. With source resistance greater than 106 k, the overall noise of the system is dominated by the Johnson noise of the resistor itself. Rev. C | Page 18 of 24 AD8551/AD8552/AD8554 OUTPUT PHASE REVERSAL Output phase reversal occurs in some amplifiers when the input common-mode voltage range is exceeded. As common-mode voltage moves outside of the common-mode range, the outputs of these amplifiers suddenly jump in the opposite direction to the supply rail. This is the result of the differential input pair shutting down and causing a radical shifting of internal voltages, resulting in the erratic output behavior. The AD855x amplifiers have been carefully designed to prevent any output phase reversal, provided both inputs are maintained within the supply voltages. If there is the potential of one or both inputs exceeding either supply voltage, place a resistor in series with the input to limit the current to less than 2 mA to ensure the output does not reverse its phase. The optimum value for the resistor and capacitor is a function of the load capacitance and is best determined empirically because actual CLOAD (CL) includes stray capacitances and may differ substantially from the nominal capacitive load. Table 5 shows some snubber network values that can be used as starting points. Table 5. Snubber Network Values for Driving Capacitive Loads CLOAD 1 nF 4.7 nF 10 nF RX 200 60 20 CX 1 nF 0.47 F 10 F POWER-UP BEHAVIOR At power-up, the AD855x settles to a valid output within 5 s. Figure 63 shows an oscilloscope photo of the output of the amplifier with the power supply voltage, and Figure 64 shows the test circuit. With the amplifier configured for unity gain, the device takes approximately 5 s to settle to its final output voltage. This turn-on response time is much faster than most other autocorrection amplifiers, which can take hundreds of microseconds or longer for their output to settle. CAPACITIVE LOAD DRIVE The AD855x family has excellent capacitive load driving capabilities and can safely drive up to 10 nF from a single 5 V supply. Although the device is stable, capacitive loading limits the bandwidth of the amplifier. Capacitive loads also increase the amount of overshoot and ringing at the output. An R-C snubber network, shown in Figure 61, can be used to compensate the amplifier against capacitive load ringing and overshoot. 5V VOUT 0V VIN 200mV p-p 01101-061 AD8551/ AD8552/ AD8554 RX 60 CX 0.47F VOUT CL 4.7nF V+ 0V 5s BOTTOM TRACE = 2V/DIV TOP TRACE = 1V/DIV 1V 01101-063 Figure 61. Snubber Network Configuration for Driving Capacitive Loads Although the snubber does not recover the loss of amplifier bandwidth from the load capacitance, it does allow the amplifier to drive larger values of capacitance while maintaining a minimum of overshoot and ringing. Figure 62 shows the output of an AD855x driving a 1 nF capacitor with and without a snubber network. 10s Figure 63. AD855x Output Behavior on Power-Up 100k VSY = 0V TO 5V VOUT 01101-064 100k AD8551/ AD8552/ AD8554 WITH SNUBBER Figure 64. AD855x Test Circuit for Turn-On Time WITHOUT SNUBBER 100mV Figure 62. Overshoot and Ringing are Substantially Reduced Using a Snubber Network Rev. C | Page 19 of 24 01101-062 VSY = 5V CLOAD = 4.7nF AD8551/AD8552/AD8554 APPLICATIONS 5 V PRECISION STRAIN GAGE CIRCUIT The extremely low offset voltage of the AD8552 makes it an ideal amplifier for any application requiring accuracy with high gains, such as a weigh scale or strain gage. Figure 65 shows a configuration for a single-supply, precision, strain gage measurement system. A REF192 provides a 2.5 V precision reference voltage for A2. The A2 amplifier boosts this voltage to provide a 4.0 V reference for the top of the strain gage resistor bridge. Q1 provides the current drive for the 350 bridge network. A1 is used to amplify the output of the bridge with the full-scale output voltage equal to 2 x (R1 + R2 ) RB where RB is the resistance of the load cell. B R2 R1 VOUT R3 R4 V2 V1 AD8551/ AD8552/ AD8554 R2 R1 x (V1 - V2) 01101-066 IF R4 R3 = R2 R1 , THEN VOUT = Figure 66. Using the AD855x as a Difference Amplifier In an ideal difference amplifier, the ratio of the resistors are set exactly equal to AV = R2 R4 = R1 R3 (19) Which sets the output voltage of the system to VOUT = AV (V1 - V2) (20) (17) Using the values given in Figure 65, the output voltage linearly varies from 0 V with no strain to 4.0 V under full strain. 5V Q1 2N2222 OR EQUIVALENT 4.0V 1k 2.5V A2 6 2 REF192 4 20k R1 17.4k R2 100 3 Due to finite component tolerance, the ratio between the four resistors is not exactly equal, and any mismatch results in a reduction of common-mode rejection from the system. Referring to Figure 66, the exact common-mode rejection ratio can be expressed as CMRR = R1R4 + 2R2 R4 + R2 R3 2R1R4 - 2R2 R3 (21) AD8552-B 12.0k 350 LOAD CELL 40mV FULL-SCALE A1 AD8552-A R3 17.4k R4 100 VOUT 0V TO 4.0V In the three-op amp, instrumentation amplifier configuration shown in Figure 67, the output difference amplifier is set to unity gain with all four resistors equal in value. If the tolerance of the resistors used in the circuit is given as , the worst-case CMRR of the instrumentation amplifier is CMRRMIN = 01101-065 1 2 R (22) NOTES 1. USE 0.1% TOLERANCE RESISTORS. V2 AD8554-A Figure 65. A 5 V Precision Strain Gage Amplifier R RG R R VOUT R R RTRIM 01101-067 3 V INSTRUMENTATION AMPLIFIER The high common-mode rejection, high open-loop gain, and operation down to 3 V of supply voltage makes the AD855x an excellent choice of op amp for discrete single-supply instrumentation amplifiers. The common-mode rejection ratio of the AD855x is greater than 120 dB, but the CMRR of the system is also a function of the external resistor tolerances. The gain of the difference amplifier shown in Figure 66 is given as R4 VOUT = V 1 R +R 4 3 R1 1 + R 2 R - V 2 2 R 1 (18) V1 AD8554-C AD8554-B VOUT = 1 + 2R (V1 - V2) RG Figure 67. A Discrete Instrumentation Amplifier Configuration Consequently, using 1% tolerance resistors results in a worstcase system CMRR of 0.02, or 34 dB. Therefore, either high precision resistors or an additional trimming resistor, as shown in Figure 67, should be used to achieve high common-mode rejection. The value of this trimming resistor should be equal to the value of R multiplied by its tolerance. For example, using 10 k resistors with 1% tolerance requires a series trimming resistor equal to 100 . Rev. C | Page 20 of 24 AD8551/AD8552/AD8554 HIGH ACCURACY THERMOCOUPLE AMPLIFIER Figure 68 shows a K-type thermocouple amplifier configuration with cold junction compensation. Even from a 5 V supply, the AD8551 can provide enough accuracy to achieve a resolution of better than 0.02C from 0C to 500C. D1 is used as a temperature measuring device to correct the cold junction error from the thermocouple and should be placed as close as possible to the two terminating junctions. With the thermocouple measuring tip immersed in a 0C ice bath, R6 should be adjusted until the output is at 0 V. Using the values shown in Figure 68, the output voltage tracks temperature at 10 mV/C. For a wider range of temperature measurement, R9 can be decreased to 62 k. This creates a 5 mV/C change at the output, allowing measurements of up to 1000C. 12V 2 R Monitor Output = R2 x SENSE R 1 x IL (23) Using the components shown in Figure 69, the monitor output transfer function is 2.5 V/A. Figure 70 shows the low-side monitor equivalent. In this circuit, the input common-mode voltage to the AD8552 is at or near ground. Again, a 0.1 resistor provides a voltage drop proportional to the return current. The output voltage is given as R VOUT = (V + ) - 2 x RSENSE x I L R 1 For the component values shown in Figure 70, the output transfer function decreases from V+ at -2.5 V/A. 3V RSENSE 0.1 IL V+ 3V 0.1F (24) REF02EZ 6 4 5.000V 0.1F R1 10.7k D1 R5 40.2k R8 124k 5V 1N4148 10F + 0.1F R1 100 3 8 K-TYPE THERMOCOUPLE 40.7V/C R4 5.62k R2 2.74k R6 200 R3 53.6 R7 453 2 S D G 1/2 AD8552 4 1 2 3 - 8 1 AD8551 + 4 M1 Si9433 MONITOR OUTPUT 01101-068 Figure 68. A Precision K-Type Thermocouple Amplifier with Cold Junction Compensation Figure 69. A High-Side Load Current Monitor V+ R2 2.49k PRECISION CURRENT METER Because of its low input bias current and superb offset voltage at single supply voltages, the AD855x is an excellent amplifier for precision current monitoring. Its rail-to-rail input allows the amplifier to be used as either a high-side or low-side current monitor. Using both amplifiers in the AD8552 provides a simple method to monitor both current supply and return paths for load or fault detection. Figure 69 shows a high-side current monitor configuration. In this configuration, the input common-mode voltage of the amplifier is at or near the positive supply voltage. The rail-torail input of the amplifier provides a precise measurement even with the input common-mode voltage at the supply voltage. The CMOS input structure does not draw any input bias current, ensuring a minimum of measurement error. The 0.1 resistor creates a voltage drop to the noninverting input of the AD855x. The output of the amplifier is corrected until this voltage appears at the inverting input. This creates a current through R1, which in turn flows through R2. The monitor output is given by VOUT Q1 V+ R1 100 1/2 AD8552 01101-070 RSENSE 0.1 RETURN TO GROUND Figure 70. A Low-Side Load Current Monitor PRECISION VOLTAGE COMPARATOR The AD855x can be operated open-loop and used as a precision comparator. The AD855x has less than 50 V of offset voltage when run in this configuration. The slight increase of offset voltage stems from the fact that the autocorrection architecture operates with lowest offset in a closed-loop configuration, that is, one with negative feedback. With 50 mV of overdrive, the device has a propagation delay of 15 s on the rising edge and 8 s on the falling edge. Ensure the maximum differential voltage of the device is not exceeded. For more information, refer to the Input Overvoltage Protection section. Rev. C | Page 21 of 24 01101-069 0V TO 5.00V (0C TO 500C) R2 2.49k AD8551/AD8552/AD8554 OUTLINE DIMENSIONS 3.20 3.00 2.80 5.00 (0.1968) 4.80 (0.1890) 3.20 3.00 2.80 PIN 1 8 5 1 5.15 4.90 4.65 4.00 (0.1574) 3.80 (0.1497) 8 1 5 4 6.20 (0.2440) 5.80 (0.2284) 4 1.27 (0.0500) BSC 0.65 BSC 0.95 0.85 0.75 0.15 0.00 0.38 0.22 0.25 (0.0098) 0.10 (0.0040) 1.10 MAX 8 0 0.80 0.60 0.40 1.75 (0.0688) 1.35 (0.0532) 0.50 (0.0196) 0.25 (0.0099) 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 45 COPLANARITY 0.10 SEATING PLANE 0.51 (0.0201) 0.31 (0.0122) 0.23 0.08 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 71. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 3.10 3.00 2.90 Figure 73. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 5.10 5.00 4.90 8 5 14 8 4.50 4.40 4.30 1 4 6.40 BSC 4.50 4.40 4.30 1 7 6.40 BSC PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX SEATING 0.20 PLANE 0.09 PIN 1 1.05 1.00 0.80 0.65 BSC 1.20 MAX 0.15 0.05 0.30 0.19 8 0 0.20 0.09 0.75 0.60 0.45 SEATING COPLANARITY PLANE 0.10 8 0 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AA COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 72. 8-Lead Thin Shrink Small Outline Package [TSSOP] (RU-8) Dimensions shown in millimeters 8.75 (0.3445) 8.55 (0.3366) 14 1 8 7 Figure 74. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters 4.00 (0.1575) 3.80 (0.1496) 6.20 (0.2441) 5.80 (0.2283) 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) SEATING PLANE 0.50 (0.0197) 0.25 (0.0098) 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 45 COMPLIANT TO JEDEC STANDARDS MS-012-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 75. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches) Rev. C | Page 22 of 24 060606-A 060506-A COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. AD8551/AD8552/AD8554 ORDERING GUIDE Model AD8551AR AD8551AR-REEL AD8551AR-REEL7 AD8551ARZ 1 AD8551ARZ-REEL1 AD8551ARZ-REEL71 AD8551ARM-R2 AD8551ARM-REEL AD8551ARMZ-R21 AD8551ARMZ-REEL1 AD8552AR AD8552AR-REEL AD8552AR-REEL7 AD8552ARZ1 AD8552ARZ-REEL1 AD8552ARZ-REEL71 AD8552ARU AD8552ARU-REEL AD8552ARUZ1 AD8552ARUZ-REEL1 AD8554AR AD8554AR-REEL AD8554AR-REEL7 AD8554ARZ1 AD8554ARZ-REEL1 AD8554ARZ-REEL71 AD8554ARU AD8554ARU-REEL AD8554ARUZ1 AD8554ARUZ-REEL1 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead TSSOP 8-Lead TSSOP 8-Lead TSSOP 8-Lead TSSOP 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP Package Option R-8 R-8 R-8 R-8 R-8 R-8 RM-8 RM-8 RM-8 RM-8 R-8 R-8 R-8 R-8 R-8 R-8 RU-8 RU-8 RU-8 RU-8 R-14 R-14 R-14 R-14 R-14 R-14 RU-14 RU-14 RU-14 RU-14 Branding AHA AHA AHA# AHA# Z = RoHS Compliant Part, # denotes RoHS compliant part may be top or bottom marked. Rev. C | Page 23 of 24 AD8551/AD8552/AD8554 NOTES (c)1999-2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C01101-0-3/07(C) Rev. C | Page 24 of 24 |
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